Integrated circuit chips have grown in size and packing density to meet user demands for more functions and greater storage capacity at lower cost. With this development, advantages in distributing power to the chip become important.
A common approach is to incorporate a power distribution network into the chip itself. However the power busses tend to be large and the chip size must be increased to accommodate them. Aside from the usual cost disadvantage an increase in the size of a chip that is already comparatively large may require an expensive, or non-standard, package design. Correct use of these tradeoffs is becoming a vital ingredient in the ability of a manufacturer to produce cost competitive advanced memory devices.
An alternative is to distribute the power off chip and introduce power (and ground) at more than one bonding site on the chip. However each new bonding site consumes a pin and it is desirable to avoid multiple pins for power and ground connections.